1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to phase change random access memory (PRAM) devices.
A claim of priority is made to Korean Patent Application No. 10-2005-0053898, filed on Jun. 22, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to heat so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by heating the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIGS. 1A and 1B illustrate a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively, and FIG. 2 is an equivalent circuit diagram of the memory cell 10 of FIGS. 1A and 1B. As shown, the memory cell 10 includes a phase-change resistive element 11 and diode D connected in series between a bit line BL and a word line WL.
It should be noted that the structure of the phase-change element 11 is presented as an example only, and that other structures may be possible. Similarly, the connections illustrated in FIGS. 1A, 1B and 2 are presented as examples only, and other configurations are possible. For example, the memory cell 10 may include the phase-change resistive element 11 and a transistor connected in series between the bit line BL and reference potential, with the transistor gated to the word line WL.
In each of FIGS. 1A and 1B, the phase-change resistive element 11 includes a top electrode 12 formed on a phase-change material 14. In this example, the top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between the phase-change material 14 and a conductive bottom electrode 18. The diode D is electrically connected between the bottom electrode 18 and the word line WL of the PRAM cell array (not shown). Specifically, in this example, the N-junction of the diode D is connected to the word line WL and the P-junction of the diode D is connected to a bit line BL via the phase-change resistive element 11.
In FIG. 1A, the phase-change material 14 is illustrated as being in its crystalline state. As mentioned previously, this means that the memory cell 10 is in a low-resistance ‘set’ state or logic 0 state. In FIG. 1B, a portion of the phase-change material 14 is illustrated as being amorphous. Again, this means that the memory cell 10 is in a high-resistance ‘reset’ state or logic 1 state.
The set and reset states of the memory cell 10 of FIGS. 1A and 1B are establish by controlling the magnitude and duration of current flow through the BEC 16. That is, as shown in FIG. 2, the memory cell 10 is activated (or accessed) by applying a LOW level voltage to the word line WL. When activated, the phase-change element is programmed according to the voltage of the bit line BL. More specifically, the bit line BL voltage is controlled to establish a programming current which causes the BEC 16 to act as a resistive heater which selectively programs the phase-change material 14 in its ‘set’ and ‘reset’ states.
FIG. 3 is a view showing the core structure of a conventional phase change memory device 300.
Referring to FIG. 3, the phase change memory device 300 includes memory cell blocks CBLK11, CBLK12, . . . , CBLKn1, and CBLKn2 each including memory cells C11 through C1n; word line driving blocks WDU11, WDU12, . . . WDUn1 and WDUn2 which drive respective word lines WL11 and WL12 . . . of the memory cell blocks CBLK11, CBLK12, . . . , CBLKn1, and CBLKn2; and bit line selection blocks YPASS11, YPASS12, . . . , YPASSn1, and YPASSn2, each of which selects bit lines BL11 through BL1n of a corresponding memory cell block CBLK11, CBLK12, CBLKn1, or CBLKn2. Also, FIG. 3 illustrates block areas which may contain a column decoder YDEC, a sense amplification circuit SA, and a write driver WD.
The operation of the phase-change memory cell 300 will be briefly described with reference to the memory cell block CBLK11. The remaining memory cell blocks CBLK12, . . . , CBLKn1, and CBLKn2 all function in a similar manner.
The word line driving block WDU11 includes a plurality of word lines driving circuits WDC11 which are responsive to first and second selection signals Si and Ai to drive the corresponding word lines WL11. The bit line selection block YPASS11 includes a plurality of bit line selection circuits BCD11 through BCD1n for selecting the corresponding bit lines BL11 through BL1n. In this example, the bit line selection circuits BCD11 through BCD1n are transistors respectively turned on/off in response to bit line selection signals Y11 through Y1n.
In order to store data in a selected memory cell C11, the bit line selection circuit BDC11 of the bit line selection block YPASS11 is activated in response to a bit line selection signal Y11. Thus, a current received from a global bit line (not shown) is applied to the selected bit line BL11.
At this time, the voltage of the word line WL11 selected by the word line driving circuit WDC11 falls to a ground voltage, and thus a current is applied to the memory cell C11 connected to the word line WL11 among memory cells connected to the selected bit line BL11.
The current changes the state of the phase change material GST of the memory cell C11 and flows to the word line driving circuit WDC11 via the diode D and the word line WL11. In this example, the word line driving circuit WDC11 functions as a logical NAND circuit which receives the first selection signal Si and the second selection signal Ai. The first selection signal Si and the second selection signal Ai may be signals obtained by decoding an address signal (not shown) for selecting a word line. If both the first and second selection signals Si and Ai are high, the corresponding word line WL11 is selected. If either or both of the first and second selection signals Si and Ai is low, the corresponding word line WL11 is not selected.
The logical NAND functionality of the word line driving circuit WDC11 is implemented by the combination of an AND device and an inverter. In the word line driving circuit WDC11 having such an inverter, a PMOS transistor and a NMOS transistor are arranged together. Accordingly, in order to prevent latch-up of the transistors, an isolation area which is larger than that defined according to a minimum design rule must be located between the PMOS transistor and the NMOS transistor. This isolation area increases the size of the word line driving circuit, and, accordingly, increases the size of the overall core area of the phase change memory device.